Design and Implementation of FPGA System to Reduce Reed- Solomon Errors

The data reliability has become an important issue in most communication and storage systems for high speed operation and mass data process. Various error correction code are provided for improving data reliability. A Reed-Solomon code is quite suitable for burst errors, but in case of random errors, it has some difficulty. For MLC NAND flash memories, BoseChaudhuriHocquenghem (BCH) codes are frequently used. BCH codes provide flexible code length and variable range of error correcting capability. However, NAND flash memory systems process with the large size of data such as a page or a block unit. Hence, BCH codes may not be appropriate for a NAND flash controller. We propose product ReedSolomon (RS) code for non-volatile NAND flash memory systems. ReedSolomon codes are the most diversely used in data storage systems, but powerful for burst errors only. In order to correct multiple random errors and burst errors, another efficient decoding algorithm is required. The product code composing of columnwise Reed-Solomon codes and row-wise ReedSolomon codes may allow decoding multiple errors beyond their error correction capability. The proposed code consists of two shortened ReedSolomon codes and a conventional ReedSolomon code. We implement the proposed coding scheme on a FPGA-based simulator with using an FPGA device. The proposed code can correct 16 symbol